| 面向单元内加速的可重构算法设计 |
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| 引用本文： | 李瑞娟.面向单元内加速的可重构算法设计[J].柳州师专学报,2014(2):133-135,132. |
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| 作者姓名： | 李瑞娟 |
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| 作者单位： | 柳州职业技术学院,广西柳州545006 |
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| 摘 要： | 为了能够在可编辑逻辑器件上设计更高速度的功能单元,提出了一种面向单元内加速的可重构算法。通过该算法能够对目标逻辑功能单元进行功能重构,并以缩短单元内部逻辑门的层数,以及单元内逻辑门的控制结构,实现单元内加速。选取了典型的可重构计算单元,分析了应用本文所设计的可重构算法对逻辑功能单元进行重构设计。测试中,经过重构设计后的计算单元,运行时间最多减少了30%。
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| 关 键 词： | 重构设计 单元 层数 加速 算法 |
Reconfigurable Algorithm Design for Unit-in Acceleration |
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| LI Ruijuan.Reconfigurable Algorithm Design for Unit-in Acceleration[J].Journal of Liuzhou Teachers College,2014(2):133-135,132. |
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| Authors: | LI Ruijuan |
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| Institution: | LI Ruijuan (Liuzhou Vocational and Technical College, Liuzhou, Guangxi, 545006 China) |
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| Abstract: | In order to design a faster function unit in programmable logic device, this paper proposes a unit-in accelerated reconfigurable algorithm. This algorithm can reconfigure the targeted logic function units, reduce the number of layers and control structure of logic gate inside the unit, realize unit-in acceleration. It selects typical reconfigurable computing units, uses the designed reconfigurable algorithm to conduct reconfigurable design in logic function unit. The speed of reconfigured computing unit can improve 18.9%. |
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| Keywords: | reconfigurable design unit layers acceleration algorithm |
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