| 高速离散余弦变换VLSI实现的可测性设计 |
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| 引用本文： | 朱华贵.高速离散余弦变换VLSI实现的可测性设计[J].科技广场,2006(8):16-17. |
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| 作者姓名： | 朱华贵 |
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| 作者单位： | 江西财经大学电子学院,南昌,330013 |
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| 摘 要： | 本文提出了一种离散余弦变换电路VLSI实现的可测试性设计。它采用基于算法结构变换的并行实现,所用乘法的数量大大减少,降低了硬件面积占用和功率消耗。为提高DCT的可靠性,在本设计中加入可测性设计方法,采用一种新的内建自测试(BIST)技术。实验表明该设计对运算器的内部结构和运算速度影响小,并具有较高的故障覆盖率。本文的方法适用于高可靠性要求下的数字信号处理的VLSI实现。
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| 关 键 词： | 离散余弦变换 算法结构变换 可测性设计 内建自测试 |
| 文章编号： | 1671-4792-（2006）8-0082-02 |
Design for Testability of a Novel High-Speed DCT in VLSI |
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| Zhu Huagui.Design for Testability of a Novel High-Speed DCT in VLSI[J].Science Mosaic,2006(8):16-17. |
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| Authors: | Zhu Huagui |
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| Institution: | School of Electronic, Jiangxi University of Finance and Economics, Nanchang 330013 |
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| Abstract: | In this paper , a VLSI implementation method of design-for-testability for DCT is presented . Thealgorithm-architecture transformation can be used to derive efficient DCT implementations where the number ofmultiplication can be reduced dramatically . It adopt a parallel architecture to reduce hardware overhead andpower consumption . To improve the testability of DCT , a novel build-in self-test technique can be adopt inthe method of design for testability . The BIST structure has a little influence on the inner multiplierstructure and its speed . The test results show that it obtains a high fault coverage . The method of the papercan be used as VLSI realization of digital signal process with high reliability. |
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| Keywords: | Discrete Cosine Transform Algorithm-Architecture Transformation Design for Testability Build-in Self-Test |
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