| 剩余数制在加法运算器设计中的应用 |
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| 引用本文： | 吴琼.剩余数制在加法运算器设计中的应用[J].鄂州大学学报,2006,13(6):26-27,40. |
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| 作者姓名： | 吴琼 |
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| 作者单位： | 鄂州大学,计算机系,湖北,鄂州,436000 |
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| 摘 要： | 加法运算器是计算机芯片设计中最基本的单元之一，二进制普遍应用于计算机算术运算，该文分析了剩余数制构造原理，论证了在加法运算器设计中用剩余数制取代二进制的可行性及优点与出现的问题。
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| 关 键 词： | 加法运算器设计 二进制 剩余数制 |
| 文章编号： | 1008-9004（2006）06-0026-02 |
| 收稿时间： | 04 10 2006 12:00AM |
| 修稿时间： | 2006-04-10 |
Surplus notational system in addition logic unit design application |
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| WU Qiong.Surplus notational system in addition logic unit design application[J].Journal of Ezhou University,2006,13(6):26-27,40. |
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| Authors: | WU Qiong |
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| Institution: | Computer Department, Ezhou University, Ezhou, Hubei 436000, China |
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| Abstract: | Addition Logic unit is one of the most basic units in a computer chip design. Binary system is generally applied to the computer arithmetic operations, this article analysed the principle of surplus notational system, and demonstrated the feasibility and advantages as well as some questions which will probably arise in the event that surplus notational system takes the place of binary system in addition logic unit design. |
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| Keywords: | addition logie unit design binary system surplus notational system |
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