| 面向流水线设计的可重构算法设计 |
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| 引用本文： | 何乃味.面向流水线设计的可重构算法设计[J].柳州师专学报,2014(1):138-140,143. |
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| 作者姓名： | 何乃味 |
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| 作者单位： | 柳州职业技术学院,广西柳州545006 |
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| 基金项目： | 2013年广西教育厅科研课题“高校《EDA技术》教学实验平台开发”（2013LX224）;柳州职业技术学院质量丁程项目“印刷电路板的设计与制作维护”（2011-A023）. |
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| 摘 要： | 为了优化在可编程逻辑器件上所设计的功能算法执行速度,提出了一种面向流水线设计的可重构算法.通过对用户预先设计的逻辑功能进行结构分析,采用标准化的流程对用户逻辑功能进行分解,自动形成适合流水线设计的可重构逻辑单元,实现面向流水线设计的可重构设计方案.应用新型的可重构算法,对选定的两组逻辑功能,分别用传统的逻辑设计方法及面向流水线设计的可重构设计方案,进行对比测试.测试结果表明:新型算法能够使逻辑功能整体运行速度,提高42.5%.
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| 关 键 词： | 可重构 流水线 逻辑芯片 功能分解 运行速度 |
A Design on Reconfigurable Algorithm Design for Pipelined Design |
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| HE Naiwei.A Design on Reconfigurable Algorithm Design for Pipelined Design[J].Journal of Liuzhou Teachers College,2014(1):138-140,143. |
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| Authors: | HE Naiwei |
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| Institution: | HE Naiwei (Liuzhou Vocational and Technical College, Liuzhou, Guangxi, 545006 China) |
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| Abstract: | In order to optimize the execution speed of function algorithm in programmable logic device, this paper presents a reconfig- urable algorithm for pipelined design. By structural analyzing of the user＇ s pre-designed logic functions, it uses standardized processes to decompose user＇ s logic function, and automatically forms reeonfigurable logic units for pipelined design, it forms a reeonfigurable pipe- lined design scheme. By taking two sets logic function, it applies the new designed algorithm respectively to traditional logic design meth- odology and reconfigurable pipelined design scheme. The comparison test shows that this new algorithm can make the logic function over- all operation speed improve 42.6%. |
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| Keywords: | reconfigurable pipeline logic chips functional decomposition operation speed |
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