| 基于功效的集成电路延时估算与优化 |
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| 引用本文： | 殷万君,白天蕊.基于功效的集成电路延时估算与优化[J].广东职业技术师范学院学报,2011(12):9-12. |
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| 作者姓名： | 殷万君 白天蕊 |
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| 作者单位： | 西南交通大学,四川成都610031 |
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| 基金项目： | 国家973计划资助项目（No.2007CB714700）.国家自然科学基金资助项目（No.60776827） |
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| 摘 要： | 本文讨论了cmos门电路延时时间的估算模型，介绍了逻辑功效对逻辑门电路的优化方法，在确定的工艺条件下，根据电路要求，可以快速确定最优的逻辑结构和晶体管的尺寸，在集成电路的设计中具有很高的应用价值．
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| 关 键 词： | 逻辑功效 寄生延时 逻辑优化 |
Time Delay Estimation and Optimization of IC Based on The Effect |
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| Yin Wanjun Bai Tianrui.Time Delay Estimation and Optimization of IC Based on The Effect[J].Journal of Guangdong Polytechnical Normal University,2011(12):9-12. |
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| Authors: | Yin Wanjun Bai Tianrui |
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| Institution: | Yin Wanjun Bai Tianrui (Southwest Jiao Tong University, Chengdu 610031, China) |
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| Abstract: | This paper discusses the time delay estimation model of the CMOS gate circuit, and introduces the logic gate circuit optimization method based on the logical effect. Under certain conditions, according to the circuit, the optimal logical structure and the size of the transistor can he quickly determind. It is valuable for the IC design. |
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| Keywords: | logical effect parasitic delay logic optimization |
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