| 基于流水线结构的可重构AES算法IP核的硬件实现(英文) |
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| 引用本文： | 李冰,夏克维,梁文丽.基于流水线结构的可重构AES算法IP核的硬件实现(英文)[J].东南大学学报,2010,26(1):21-25. |
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| 作者姓名： | 李冰 夏克维 梁文丽 |
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| 作者单位： | 东南大学集成电路学院; |
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| 摘 要： | 为了提高AES算法中IP核数据的吞吐量并同时减小硬件资源的占用,以达到速度和面积的折中实现,采用混合流水线结构和可重构技术完成了IP核的设计.该设计包括在同一个混合流水线结构的流程中实现了AES算法的加密和解密过程;根据有限域的性质,对AES算法中的Sbox盒进行了优化;结合可重构技术,完成了对AES轮变换的主要构件ShiftRow和MixColumn的优化.本设计在Xilinx Virtex2p xc2vp20-7 FPGA器件上完成,其数据吞吐量达到2.58Gbit/s,所需组合逻辑仅为3 233块,通过与同型号器件上的其他设计进行对比,实现了速度和面积的折中,在吞吐量和面积上都得到了比较理想的结果.
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| 关 键 词： | AES算法 可重构 流水线 有限域 轮变换 |
Reconfigurable implementation of AES algorithm IP core based on pipeline structure |
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| Li Bing,Xia Kewei,Liang Wenli.Reconfigurable implementation of AES algorithm IP core based on pipeline structure[J].Journal of Southeast University(English Edition),2010,26(1):21-25. |
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| Authors: | Li Bing Xia Kewei Liang Wenli |
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| Institution: | School of Integrated Circuits;Southeast University;Nanjing 210096;China |
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| Abstract: | In order to improve the data throughput of the advanced encryption standard (AES) IP core while reducing the hardware resource consumption and finally achieving a tradeoff between speed and area, a mixed pipeline architecture and reconfigurable technology for the design and implementation of the AES IP core is proposed. The encryption and decryption processes of the AES algorithm are achieved in the same process within the mixed pipeline structure. According to the finite field characterizations, the Sbox i... |
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| Keywords: | advanced encryption standard(AES)algorithm reconfigurable pipeline finite field round transformation |
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