| 用Verilog HDL语言实现并串、串并接口的转换 |
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| 引用本文： | 夏军波.用Verilog HDL语言实现并串、串并接口的转换[J].钦州学院学报,2006,21(3):54-56. |
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| 作者姓名： | 夏军波 |
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| 作者单位： | 解放军防空兵指挥学院,河南,郑州,450052 |
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| 摘 要： | 在微型计算机系统中,CPU与外部的基本通信方式有两种,一种是并行通信即数据的各位同时传送,其优点是传输速度较快,但数据有多少位就需要多少条传送线;而串行通信中数据一位一位顺序传送,能节省传送线.用Verilog HDL语言实现了串并、并串通信接口之间的转换.
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| 关 键 词： | Verilog HDL语言 串行通信 并行通信 |
| 文章编号： | 1008-5629(2006)03-0054-03 |
| 修稿时间： | 2006年4月28日 |
On How to Reach the Interface Transfers of Parallel-series and Series-parallel by the Language Performs of Verilog HDL |
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| XIA Jun-bo.On How to Reach the Interface Transfers of Parallel-series and Series-parallel by the Language Performs of Verilog HDL[J].Journal of Qinzhou University,2006,21(3):54-56. |
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| Authors: | XIA Jun-bo |
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| Abstract: | In the system of mini-computer exist two kinds of CPU and external basic communication mode: one is the parallel communication, i.e.,the simultaneous communication of digits with the advantage of faster communicating speed but the equality of digits and communicating lines;the other is the series communication with the digit to digit sequence and saving of communication lines.The paper suggests that it is feasible to reach the interface transfers of the parallel-series and the series-parallel by the language performs of Verilog HDL. |
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| Keywords: | the language performs of Verilog HDL parallel communication series communication |
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