| SoC中存储器测试技术的研究 |
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| 引用本文： | 柴华,谈恩民,江志强.SoC中存储器测试技术的研究[J].大众科技,2012,14(3):33-35,39. |
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| 作者姓名： | 柴华 谈恩民 江志强 |
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| 作者单位： | 桂林电子科技大学电子工程与自动化学院,广西桂林,541004 |
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| 摘 要： | 随着集成电路规模的不断扩大,基于IP核复用的SoC设计技术被广泛应用,但是由于IP核的来源不同,使得SoC的测试变得越来越困难。IEEE Std 1500给IP核提供商与用户之间提供了标准的测试接口,简化核测试信息的复用。文章基于此标准设计了SoC中存储器的Wrapper测试壳结构和BIST控制器,以DRAM和SRAM为测试对象进行验证,结果表明了在不同测试指令和故障模式下,测试壳和控制器的有效性。
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| 关 键 词： | SoC存储器 IEEE Std 1500 测试外壳 BIST |
Study on Memory Testing Technology of the SoC |
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| Abstract: | With the constant expansion of integrated circuits,the design technology of SoC based on reusing IP cores is widely used,but the SoC testing is becoming increasingly difficult due to different sources of IP cores.IEEE Std 1500 provides a standard test interface for the IP cores providers and users,so the reusing of core test information is simplified.This paper gives a design for the Wrapper architecture and controller of the SoC memory is based on the IEEE Std 1500,and takes the DRAM and SRAM as the test objects.Finally we verify the test wrapper and controller’s efficiency under different test instructions. |
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| Keywords: | SoC memory IEEE Std 1500 Wrapper BIST |
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