| Physical design method of MPSoC |
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| 作者姓名： | LIU Peng XIA Bing-jie TENG Zhao-wei |
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| 作者单位： | Department of Information Science ＆ Electronic Engineering, Zhejiang University, Hangzhou 310027, China |
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| 基金项目： | Project supported by the Hi-Tech Research and Development Pro-gram (863) of China (No. 2002AA1Z1140)，the Fok Ying TongEducation Foundation (No. 94031), China |
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| 摘 要： | Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel di- agonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Custom clock network con- taining hand-adjusted buffers and variable routing rules is constructed to realize balanced synchronization. Effective power plan considering both IR drop and electromigration achieves high utilization and maintains power integrity in our MediaSoC. Using such methods, deep sub-micron design challenges are managed under a fast prototyping methodology, which greatly shortens the design cycle.
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| 关 键 词： | 片上多处理器系统 物理设计方法 平面布置图 快速原型制作 |
| 收稿时间： | 2006-09-21 |
| 修稿时间： | 2006-12-27 |
Physical design method of MPSoC |
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| LIU Peng XIA Bing-jie TENG Zhao-wei.Physical design method of MPSoC[J].Journal of Zhejiang University Science,2007,8(4):631-637. |
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| Authors: | Peng Liu Bing-jie Xia Zhao-wei Teng |
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| Institution: | (1) Department of Information Science & Electronic Engineering, Zhejiang University, Hangzhou, 310027, China |
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| Abstract: | Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel di- agonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Custom clock network con- taining hand-adjusted buffers and variable routing rules is constructed to realize balanced synchronization. Effective power plan considering both IR drop and electromigration achieves high utilization and maintains power integrity in our MediaSoC. Using such methods, deep sub-micron design challenges are managed under a fast prototyping methodology, which greatly shortens the design cycle. |
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| Keywords: | Physical design Fast prototyping Floorplan Clock tree synthesis (CTS) Power plan Multiprocessor system-onchip (MPSoC) |
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