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单通道神经信号再生集成电路
引用本文:李文渊,王志功.单通道神经信号再生集成电路[J].东南大学学报,2008,24(2):155-158.
作者姓名:李文渊  王志功
作者单位:东南大学射频与光电集成电路研究所 南京210096
摘    要:将利用分立器件设计的4通道神经信号再生电子系统成功地应用于大鼠和家兔的活体动物实验,再生了它们的神经信号.采用相同的原理,用CSMC0.6μm CMOS工艺设计实现了单通道神经信号再生集成电路.电路由增益可调的神经信号探测电路、缓冲器和神经功能电激励电路构成.电路采用±2.5V双电源电压供电.芯片尺寸为1.42mm×1.34mm.在片测试电路的静态功耗小于10mW,输出电阻为118mΩ,3dB带宽大于30kHz,增益在50~90dB可调.电路芯片与卡肤电极、针状双体电极一起,用于大鼠的神经信号再生的活体动物实验,成功地再生了大鼠的坐骨神经和脊髓神经信号.

关 键 词:神经信号再生  功能电激励  集成电路  电极  CMOS工艺

Integrated circuit for single channel neural signal regeneration
Li Wenyuan,Wang Zhigong.Integrated circuit for single channel neural signal regeneration[J].Journal of Southeast University(English Edition),2008,24(2):155-158.
Authors:Li Wenyuan  Wang Zhigong
Institution:Li Wenyuan Wang Zhigong (Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China)
Abstract:Based on the 4-channel neural signal regeneration system which is realized by using discrete devices and successfully used for in-vivo experiments on rats and rabbits, a single channel neural signal regeneration integrated circuit (IC)is designed and realized in CSMC ' s 0. 6 μm CMOS ( complementary metal-oxide-semiconductor transistor ) technology. The IC consists of a neural signal detection circuit with an adjustable gain, a buffer, and a function electrical stimulation (FES) circuit. The neural signal regenerating IC occupies a die area of 1.42 mm × 1.34 mm. Under a dual supply voltage of ±2. 5 V, the DC power consumption is less than 10 mW. The on-wafer measurement results are as follows: the output resistor is 118 ml), the 3 dB bandwidth is greater than 30 kHz, and the gain can be variable from 50 to 90 dB. The circuit is used for in-vivo experiments on the rat' s sciatic nerve as well as on the spinal cord with the cuff type electrode array and the twin-needle electrode. The neural signal is successfully regenerated both on a rat' s sciatic nerve bundle and on the spinal cord.
Keywords:neural signal regeneration  function electricalstimulation  integrated circuit  electrode  CMOS technology
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