| 带Cache和精确中断响应的CPU设计 |
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| 引用本文： | 刘秋菊,李飞,刘书伦.带Cache和精确中断响应的CPU设计[J].实验室研究与探索,2012,31(3):68-74,95. |
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| 作者姓名： | 刘秋菊 李飞 刘书伦 |
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| 作者单位： | 1. 重庆大学自动化学院,重庆400044;济源职业技术学院信息工程系,河南济源459000
2. 济源职业技术学院信息工程系,河南济源,459000 |
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| 基金项目： | 国家自然科学基金，河南省科技厅科技攻关项目 |
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| 摘 要： | 提出了带Cache和精确中断响应的CPU设计方案,实现指令集MIPS中选取15条指令作为本CPU的基本指令.采用基本5步流水线CPU设计,给出了指令Cache、数据Cache和精确中断响应的设计与实现.测试结果表明,该方案符合设计要求.
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| 关 键 词： | 5步流水线 指令Cache 精确中断响应 CPU设计 |
Design of CPU with Cache and Precise Interruption Response |
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| LIU Qiu-ju
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LI-Fei
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LIU Shu-lun.Design of CPU with Cache and Precise Interruption Response[J].Laboratory Research and Exploration,2012,31(3):68-74,95. |
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| Authors: | LIU Qiu-ju LI-Fei LIU Shu-lun |
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| Institution: | 2(College of Automation,Chongqing University,Chongqing 400044;Information Engineering Department, Jiyuan Vocational and Technical College,Jiyuan He’nan 459000,China) |
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| Abstract: | In this paper the design of CPU with Cache and precise interruption response was proposed.15 of the MIPS instruction set were selected as the basic instruction for the CPU.By using 5 stage pipeline,the instruction Cache,data Cache and precise interruption response were realized.The test results show that the scheme meets the design requirements. |
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| Keywords: | 5 stage pipeline instruction Cache precise interruption response design of CPU |
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