共查询到20条相似文献，搜索用时 31 毫秒
1.
Compared with traditional charge coupled device(CCD) imagers, CMOS image sensor (CIS) usingphotodiode to detectphoto signal has the advantages ofhigh photo-sensitivity, reduced blooming, highspeed, integrating signal processing circuit on chip,and lowpower and system cost[1,2]. But fixed patternnoise (FPN) caused by the mismatch in pixels or col-umns circuit severely limits image quality (1 mV—30mV)[3]. FPN is spatial and does not change betweenframes, so it is difficult to be eliminate… 相似文献
2.
A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors. 相似文献
3.
基于Jazz工艺,提出一种线性可控全集成Si Ge Bi CMOS驱动放大器（DRA）,实现多种可调功率增益放大作用。电路采用全差分共射共基结构,通过调节CMOS电流镜偏置电路和Si Ge-HBT管尺寸以及3bit控制位,实现1d B步长的可控增益。仿真结果显示：在10μA的带隙基准电流源以及3.3V的电源电压下,DRA实现八种可调功率增益,其线性度指标即输出1d B压缩点OP1d B〉3d Bm,电路供电电流〈10m A,且电路输入输出匹配良好（S11与S22均小于-19d B）。 相似文献
4.
We present a new sense amplifier circuit for EEPROM memory. The topology of the sense amplifier uses a voltage sensing method, having low cost and low power consumption as well as high reliability. The sense amplifier was implemented in an EEPROM realized with an SMIC 0.35-μm 2P3M CMOS embedded EEPROM process. Under the condition that the power supply is 3.3 V, simulation results showed that the charge time is 35 ns in the proposed sense amplifier, and that the maximum average current consumption during the read period is 40 μA. The novel topology allows the circuit to function with power supplies as low as 1.4 V. The sense amplifier has been implemented in 2-kb EEPROM memory for RFID tag IC applications, and has a silicon area of only 240 μm^2. 相似文献
5.
Guoxuan Qin Mengmeng Jin Guoping Tu Yuexing Yan Laichun Yang Yanmeng Xu Jianguo Ma 《天津大学学报(英文版)》2017,23(2):168-175
A 0.18 μm CMOS low noise amplifier(LNA) by utilizing noise-canceling technique was designed and implemented in this paper. Current-reuse and self-bias techniques were used in the first stage to achieve input matching and reduce power consumption. The core size of the proposed CMOS LNA circuit without inductor was only 128 μm 9226 μm. The measured power gain and noise figure of the proposed LNA were 20.6 and 1.9 dB,respectively. The 3-dB bandwidth covers frequency from 0.1 to 1.2 GHz. When the chip was operated at a supply voltage of 1.8 V, it consumed 25.69 mW. The high performance of the proposed LNA makes it suitable for multistandard low-cost receiver front-ends within the above frequency range. 相似文献
6.
基于集成运放NE5532设计而成的一种低频功率放大器,由直流稳压电源、电压放大电路、MOS管功率放大级电路、带阻滤波电路及数据采集显示模块五部分组成,其主要功能是将10Hz-50KHz的低频小信号放大,输出功率大于5W且波形无明显失真,并将系统的输出功率、直流电源的供给功率和整机效率实时显示出来。 相似文献
7.
为了放大微弱的高频信号,需要使用LC谐振放大器。以三极管等分立元件构建的单调谐放大器,具有功耗小,噪声低等优点。三级谐振放大器级联实现较大的增益,级间通过高频变压器互感耦合,便于调整谐振频率,并减少损耗。经测试,本LC谐振放大器放大中心谐振频率15．1MHz,偏差100kHz,-3dB带宽300kHz,实现80dB的放大倍数,功耗324mW。输入50μV微弱信号时,输出无明显失真。结果表明,该LC谐振放大器具有低噪声、低功耗、高增益等优点。 相似文献
8.
蔡惠玲 《岳阳职业技术学院学报》2012,(3):84-86
设计一种3.3V的低功耗轨到轨CMOS运放,输入级采用差分NMOS和差分PMOS共同作用,实现大的跨导。基于CSMC的0.35um 3.3V工艺模型,利用spectre软件对电路进行仿真。在电源电压3.3V,MOS管采用低开启的LVNMOS和LVPMOS,电阻负载为10K,电容负载为50pF的情况下,运放在整个共模范围内总跨导变化仅2.4%,电压增益变化仅为1.7%,直流开环增益为109dB,增益带宽积为8.4MHz,相位裕度为71,功耗为204uW。 相似文献
9.
An error correction technique to achieve a 14-bit successive approximation register analog-to-digital converter（SAR ADC） is proposed. A tunable split capacitor is designed to eliminate the mismatches caused by parasitic capacitors. The linearity error of capacitor array caused by process mismatch is calibrated by a novel calibration capacitor array that can improve the sampling rate. The dual-comparator topology ensures both the speed and precision of the ADC. The simulation results show that the SAR ADC after calibration achieves 83.07 dB SNDR and 13.5 bit ENOB at 500 kilosamples/s. 相似文献
10.
A 130 nm CMOS complementary-conducting-strip transmission line(CCS-TL)based multi-stage amplifier beyond 100 GHz was presented in this paper. Different structural parameters were investigated to achieve higher quality factor for the matching circuits. Moreover, CCS-TL based Marchand balun was implemented to achieve higher output power. The measured small signal gain was higher than 5 d B from 101 GHz to 110 GHz. DC power consumption was 67.2 mW with V_D=1.2 V, and the chip size including contact PADs was 1.12 mm×0.81 mm. 相似文献
11.
提出了一种带有冗余项的多行选址驱动算法及电路实现方案,其适用于液晶显示驱动芯片。算法通过在行调制矩阵中增加冗余行,在显示数据矩阵中增加冗余数据,从而减少了列驱动电平数。此外,还提出了本算法的实现电路。实验结果表明,在液晶显示驱动芯片中,该算法能降低30%的驱动功耗。 相似文献
12.
基于阈值电压的负温度特性以及热电压的正温度特性,给以适当的权重后把它们相加,提出了一个零温度系数的基准电压电路。该器件由工作在亚阈值区的CMOS晶体管组成,不包含电阻和双极晶体管。采用3支路电流基准结构替代共源共栅结构和嵌入式运算放大器,具有芯片面积小和功耗低的优点。仿真结果表明,在标准0.18μmCMOS工艺下,该电路可在0.75 V电源电压下工作,输出电压为563 mV。在-40~125℃范围内,电压温度系数仅为17.5×10^-6/℃。电源电压范围在1.2~1.8 V时线性灵敏度为569.5×10^-6/V,电源抑制比可达到66.5 dB@100 Hz,最高功耗仅为187.4 nW。 相似文献
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14.
介绍了一种应用于DRM/DAB频率综合器的宽带低相位噪声低功耗的CMOS压控振荡器.为了获得宽工作频带和大调谐范围,在LC谐振腔里并联一个开关控制的电容阵列.所设计的压控振荡器应用中芯国际的0.18μm RF CMOS工艺进行了流片实现.包括测试驱动电路和焊盘,整个芯片面积为750μm×560μm.测试结果表明,该压控振荡器的调谐范围为44.6%,振荡频率范围为2.27～3.57GHz.其相位噪声在频偏为1MHz时为-122.22dBc/Hz.在1.8V的电源电压下,其核心的功耗为6.16mW. 相似文献
15.
设计制作了一个太阳能充电控制器,可实现75 W太阳能电池板对蓄电池的可靠充电。主要采用Cuk电路和光耦电压反馈,并利用TL494实现PWM控制,LM393加互补功放实现驱动。通过MSP430单片机和1602液晶进行电压采样和显示。经实验论证,本方案基本完成了设计预期。 相似文献
16.
以MSP430F135单片机作为测量和显示的核心部件,采用两级前置放大电路、功率放大电路、带阻滤波电路、电流转换电路（功率测量电路）等组成一个低频功率放大器电路系统。测试结果表明,该系统能实现信号功率放大功能,具有输出噪声低、工作频带宽（10 Hz~50 kHz）、输出效率较高的特点。 相似文献
17.
论述了基于AT89C51单片机的低频功率放大器的设计与实现。采用电压放大电路、功率放大电路和稳压电源电路构成功率放大器的主体,配以高精度采样电阻及12位A/D转换器,实现了通频带30Hz～50kHz范围内的低频放大,保证了失真度小于1.2%,具有较高的精度与稳定性。实验结果表明电路功能和性能指标均已达到设计要求。 相似文献
18.
将利用分立器件设计的4通道神经信号再生电子系统成功地应用于大鼠和家兔的活体动物实验,再生了它们的神经信号．采用相同的原理,用CSMC0．6μm CMOS工艺设计实现了单通道神经信号再生集成电路．电路由增益可调的神经信号探测电路、缓冲器和神经功能电激励电路构成．电路采用±2．5V双电源电压供电．芯片尺寸为1．42mm×1．34mm．在片测试电路的静态功耗小于10mW,输出电阻为118mΩ,3dB带宽大于30kHz,增益在50～90dB可调．电路芯片与卡肤电极、针状双体电极一起,用于大鼠的神经信号再生的活体动物实验,成功地再生了大鼠的坐骨神经和脊髓神经信号． 相似文献
19.
蔡顺燕 《四川教育学院学报》2014,(11):110-113
设计了一种输入电压为5.5V～25V,输出电压为5V的直流稳压电源及其漏电保护装置系统.直流稳压电源模块采用达林顿管TIP42、OP07运算放大器及三极管构成一个深度负反馈稳压电路.输出电压经ADS1286转换为数字量后送入单片机采样输出电压,经霍尔电流传感器CSM002A、跟随器OP07后,送入ADS1286,转换为数字量后送入单片机采样负载电流.由软件程序计算功率,并在液晶上显示.通过采样负载电流与总电流的差值实现漏电检测,并进行漏电保护.经测试,系统电压调整率Su≤1％,负载调整率SL≤1％,5.5V ～ 25V输入,输出为5±0.05V. 相似文献
20.
An addition scheme applicable to time-delay integration (TDI) CMOS image sensor is proposed,which adds signals in the charge domain in the pixel array.A two-shared pixel structure adopting two-stage charge transfer is introduced,together with the rolling shutter with an undersampling readout timing.Compared with the conventional TDI addition methods,the proposed scheme can reduce the addition operations by half in the pixel array,which decreases the power consumption of addition circuits outside the pixel array.The timing arrangement and pixel structure are analyzed in detail.The simulation results show that the proposed pixel structure can achieve the charge addition with negligible nonlinearity,therefore the power consumption of the periphery addition circuits can be reduced by half theoretically. 相似文献