共查询到18条相似文献，搜索用时 687 毫秒
1.
徐思成 《实验室研究与探索》2011,30(8)
设计了一个基于TSMC0.18 μmCMOS工艺的2.0 GHz全差分CMOS低噪声放大器.根据电路结构特点,对LNA进行功耗约束下的噪声优化,以选取最优的晶体管栅宽;采用在输入级增加电容和选择小值LC并联网作为差分电路的负载的方法,在改善输入匹配网络特性的同时,提高了电路的增益.仿真结果表明该放大器较好地满足了小信号放大器的指标要求,可以用于射频输入电路的前端. 相似文献
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为了提高接收机的性能,基于台积电公司0.18 μm CMOS工艺设计了低噪声放大器.从晶体管模型出发,分析了阻抗匹配,采用源端负反馈和提高输入匹配的电感Q值来降低噪声.通过电路的共源共栅结构搭配电路,消除密勒电容,提高电路性能. 相似文献
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陆伟艳 《南宁师范高等专科学校学报》2008,25(4):119-120
低噪声放大器是射频前端的关键部件。针对超宽带低噪声放大器实际应用中对带宽、增益、噪声等要求,文中基于多级反馈技术,用AglientEDA工具ADS进行全面的仿真分析和优化设计。测试结果表明,实际测得的指标能与仿真结果较好的吻合．实现了一种较好的超宽带、低噪声、带内平坦度好和良好端口匹配的高效宽带放大器。 相似文献
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唐学锋 《湖州师范学院学报》2012,34(1):53-56
基于0.18μm CMOS工艺,采用共源共栅源极电感负反馈结构,设计了一个针对蓝牙接收机应用的2.4GHz低噪声放大器(LNA)电路.分析了电路的主要性能,包括阻抗匹配、噪声、增益与线性度等,并提出了相应的优化设计方法.仿真结果表明,该放大器具有良好的性能指标,在5.4mW功耗下功率增益为18.4dB,噪声系数为1.935dB,1dB压缩点为-14dBm. 相似文献
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赵华峰 《渭南师范学院学报》2014,(15):18-22
负反馈放大电路的计算在电路分析和设计时经常用到,为此首先进行负反馈放大电路计算的理论分析,给出常用的计算方法和近似估算方法,然后对一个常用的带负反馈的放大电路在Multisim12上进行仿真,仿真时要考虑反馈网络对基本放大器输入、输出端的负载效应的影响,经过对仿真波形和数据的分析计算,表明闭环和开环仿真得到的增益之间的关系、通频带之间的关系都和理论分析吻合得很好。 相似文献
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林蔚 《Journal of Zhangzhou Technical Institute》2008,10(2):8-12
本文设计的轨对轨运算放大器主要是为TFT-LCD的驱动电路提供驱动电压,输入采用电流补偿稳定运算放大器在整个输入共模范围内的跨导,采用AB类的输出方法提高运算放大器的输出范围,并对典型性能及参数进行仿真分析。 相似文献
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熊晓君 《实验室研究与探索》2006,25(4):430-431,453
以CMOS运放LMC6035构成的前置放大器和有源高通-低通滤波器为主要部件的心电放大器,可实现输出电压高增益、低噪声、高灵敏度,保证心电信号清晰稳定,满足临床监护以及病理分析的要求。在设计过程中运用电子线路CAD仿真软件对心电放大器进行功能分析,获得电路的技术指标,再进行参数修改和电路优化设计,从而可快速、精确地评价电路设计的正确性,节省实际测试费用,缩短设计开发周期。 相似文献
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介绍了单片集成MEA系统和用于该系统的神经元信号探测电路和激励电路,基本单元电路是低功耗、低噪声、高增益和小版图尺寸的运算放大器.详细讨论了探测电路、激励电路和基本单元运算放大器的设计.神经元信号探测电路版图面积290 μm×400 μm,功耗2.02 mw,等效输入噪声17.72 nV/Hz,增益60.5 dB,输出电压摆幅-2.48～+2.5 V.激励电路版图面积130μm×290 μm,功耗740μW,输出电压摆幅-2.5～2.04 V.参数表明这2种电路适用于单片集成MEA系统.探测电路和单片集成MEA系统已经流片.探测电路的测试结果表明电路工作正常. 相似文献
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激光陀螺光电检测电路的低噪声设计 总被引：1，自引：0，他引：1
依据低噪声电路理论，利用低噪声场效应管与集成运算放大器组成复合式光电检测电路，有效地解决了探测器与负载的噪声匹配问题。实验证明：该电路具有较高的灵敏度，可以满足激光陀螺的实用要求。 相似文献
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Guoxuan Qin Mengmeng Jin Guoping Tu Yuexing Yan Laichun Yang Yanmeng Xu Jianguo Ma 《天津大学学报(英文版)》2017,23(2):168-175
A 0.18 μm CMOS low noise amplifier(LNA) by utilizing noise-canceling technique was designed and implemented in this paper. Current-reuse and self-bias techniques were used in the first stage to achieve input matching and reduce power consumption. The core size of the proposed CMOS LNA circuit without inductor was only 128 μm 9226 μm. The measured power gain and noise figure of the proposed LNA were 20.6 and 1.9 dB,respectively. The 3-dB bandwidth covers frequency from 0.1 to 1.2 GHz. When the chip was operated at a supply voltage of 1.8 V, it consumed 25.69 mW. The high performance of the proposed LNA makes it suitable for multistandard low-cost receiver front-ends within the above frequency range. 相似文献
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INTRODUCTIONRecently ,thehighfrequencyperformanceofCMOShavebeenimprovedsignificantlyinthelowgigahertzfrequencybands,makingitagoodcandidatefortheintegrationofbothdigitalandanalogchips.However,performances,suchasnoiseandlinearitycharacteristics,mustbeana ly… 相似文献
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Noise and linearity performances are critical characteristics for radio frequency integrated circuits (RFICs), especially
for low noise amplifiers (LNAs). In this paper, a detailed analysis of noise and linearity for the cascode architecture, a
widely used circuit structure in LNA designs, is presented. The noise and the linearity improvement techniques for cascode
structures are also developed and have been proven by computer simulating experiments. Theoretical analysis and simulation
results showed that, for cascode structure LNAs, the first metallic oxide semiconductor field effect transistor (MOSFET) dominates
the noise performance of the LNA, while the second MOSFET contributes more to the linearity. A conclusion is thus obtained
that the first and second MOSFET of the LNA can be designed to optimize the noise performance and the linearity performance
separately, without trade-offs. The 1.9GHz Complementary Metal-Oxide-Semiconductor (CMOS) LNA simulation results are also
given as an application of the developed theory. 相似文献
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给出了一个应用于无线局域网WLAN802.11a的中低噪声、高增益的下变频器.该下变频器采用高中频的结构,输入的射频频率(RF)、本振(LO)频率和输出的中频频率(IF)分别为5.15 ～5.35,4.15 ～4.35和1GHz.为了提高混频器的线性度,电路采用了伪差分的吉尔伯特结构和源极电阻负反馈技术;为了获得低的噪声系数,混频器采用电流源注入技术和LC谐振电路作为负载.此外,采用了一种改进的源极跟随器输出缓冲电路,在不恶化其他性能的情况下混频器可以达到较高的增益.该芯片采用0.18μm RF CMOS工艺制作,包含所有焊盘在内的芯片尺寸为580μm×1 185μm.测试结果表明:在1.8V电源电压下,消耗电流为3.8mA,转换增益为10.1dB,输入1dB压缩点为-3.5dBm,输入三阶截点为5.3dBm,单边带(SSB)噪声系数(NF)为8.65dB. 相似文献
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A wideband dual-feedback low noise amplifier(LNA) was analyzed, designed and implemented using SiGe heterojunction bipolar transistor(HBT) technology. The design analysis in terms of gain, input and output matching, noise and poles for the amplifier was presented in detail. The area of the complete chip die, including bonding pads and seal ring, was 655 μm×495 μm. The on-wafer measurements on the fabricated wideband LNA sample demonstrated good performance: a small-signal power gain of 33 dB with 3-dB bandwidth at 3.3 GHz was achieved;the input and output return losses were better than-10 dB from 100 MHz to 4 GHz and to 6 GHz, respectively; the noise figure was lower than 4.25 dB from 100 MHz to 6 GHz; with a 5 V supply, the values of OP1 dB and OIP3 were1.7 dBm and 11 dBm at 3-dB bandwidth, respectively. 相似文献
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Electrical discharge machining （EDM） process, at present is still an experience process, wherein selected parameters are often far from the optimum, and at the same time selecting optimization parameters is costly and time consuming. In this paper, artificial neural network （ANN） and genetic algorithm （GA） are used together to establish the parameter optimization model. An ANN model which adapts Levenberg-Marquardt algorithm has been set up to represent the relationship between material removal rate （MRR） and input parameters, and GA is used to optimize parameters, so that optimization results are obtained. The model is shown to be effective, and MRR is improved using optimized machining parameters. 相似文献
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A high-speed dual-modulus divide-by-32/33 prescaler has been developed using 0.25μm CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed prescaler can operate at high frequency with a low-power consumption. Based on the 2.5 V, 0.25μm CMOS model, simulation results indicate that the maximum input frequency of the prescaler is up to 3.2 GHz. Running at 2.5 V, the circuit consumes only 4.6 mA at an input frequency 2.5 GHz. 相似文献